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data sheet rev.1.0 30.05.2012 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 1 ch C 9552 bronschhofen fax: +41 (0) 71 9 13 03 15 email: info@swissbit.com of 13 512mb ddr1 C sdram so - dimm 200 pin so - dimm sdn06464k1b f1mt - 50 r 512mb ddr pc3200 tsop techn ology rohs compliant features: ? ? ddr - sdram component base: micron mt46v64m8t37z ? dd 2.5v 0.2v, v dd q 2.5v 0.2v ? ? ? ? ? ? ? ? ? operating temperature (ambient) standard grade 0c to 70c grade e 0c to 85c* grade i - 25 c to 85c* grade w - 40c to 85c* operating humidity 1 0% to 90% relative humidity, noncondensing ? operating pressure 105 to 69 kpa (up to 10000 ft.) ? storage temperature - 55c to 100c ? storage humidity 5% to 95% relative humidity, noncondensing ? storage pressure 1682 psi (up to 5000 ft.) at 50c opti ons: ? ? ? a ) 0c to 70c grade e (t a ) 0c to 85c grade i (t a ) - 25 c to 85c grade w (t a ) - 40c to 85c features: ? 20 0 - pin 64 - bit small outline, dual - in - line double data rate synchronous dram module ? ddr - sdram component base micron mt46v64m8p - 5b die rev.: f ? dd = 2 . 5 v 0.2v, v ddq 2 . 5 v 0.2v ? ? ? ? ? ? ? ? ? C ck ? ? ? ? ? ? figure 1: mechanical dimensions
data sheet rev.1.0 30.05.2012 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 2 ch C 9552 bronschhofen fax: +41 (0) 71 9 13 03 15 email: info@swissbit.com of 13 this swissbit module family is industry standard 200 - pin 8 - byte double date rate synchronous sdram small outline d ual - in - line memory modules (so - dimms), which are organized as x64 high speed memory arrays designed for use in non - parity applications. these so - dimms are assembled in tsop technology. the passive devices and the eeprom are smd components. the so - dimms use serial presence detects (spd) implemented via serial eeprom using the two - pin - i 2 c protocol. the first 128 bytes are utilized by the so - dimm manufacturer and the second 128 bytes are available to the end user. all swissbit so - dimms provide a high performan ce, flex ible 8 - byte interface in a 67.6 mm long footprint. all modules of the extended temperature grade have seen special tests during the manufacturing process to ensure proper operation according to the field of operation as stated in the environmental c onditions. module configuration organization ddr sdrams used row addr. bank select col. addr. refresh module dimensions in mm 64m x 64 8 x 64m x 8 13 ba0, ba1 11 8k 67.60 x 3 1 . 75 x 3.80 max product spectrum part number module density transfer rate m emory clock/data bit rate latency sdn06464k1b f1mt - 50[ e/i/ w]r 512mb 3.2 gb/s 5.0ns / 400mt/s 32 00 - 3 0 33 sdn06464k1b f1mt - 60[ e/i/ w]r 512mb 2.7 gb/s 6.0ns / 333mt/s 2700 - 2533 pin name a0 - 9, a11 C a12 address inputs a10/ap address input/autoprecharge ba0, ba1 bank selects dq0 C dq63 data input/output dm0 - dm7 data masks /ras row address strobe /cas column address strobe /we read / write enable cke0 clock enable ck0 C ck2 clock inputs, positive line /ck0 C /ck2 clock inputs, negative line dqs0 - dqs7 data strobes
data sheet rev.1.0 30.05.2012 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 3 ch C 9552 bronschhofen fax: +41 (0) 71 9 13 03 15 email: info@swissbit.com of 13 /s0 chip select v dd power (2.5v 0.2v) v ddq power (2.5v 0.2v) v ddid vdd, vddq level detection v ddspd spd power v ref input/output reference vss ground scl clock for presence detect sda serial data out for presence detect nc no connection pin configuration pin # front side pin # back side pin # front side pin # back side 1 vref 2 vref 101 a9 102 a8 3 vss 4 vss 103 vss 104 vss 5 dq0 6 dq4 105 a7 106 a6 7 dq1 8 dq5 107 a5 108 a4 9 vdd 10 vdd 109 a3 110 a2 11 dqs0 12 dm0 111 a1 112 a0 13 dq2 14 dq6 113 vdd 114 vdd 15 vss 16 vss 115 a10/ap 116 ba1 17 dq3 18 dq7 117 ba0 118 /ras 19 dq8 20 dq12 119 /we 120 /cas 21 vdd 22 vdd 121 /s0 122 nc ( /s1 ) 23 dq9 24 dq13 123 nc (a13) 124 nc 25 dqs1 26 dm1 125 vss 126 vss 27 vss 28 vss 127 dq32 128 dq36 29 dq10 30 dq14 129 dq33 130 dq37 31 dq11 32 dq15 131 vdd 132 vdd 33 vdd 34 vdd 133 dqs4 134 dm4 35 ck0 36 vdd 135 dq34 136 dq38 37 /ck0 38 vss 137 vss 138 vss 39 vss 40 vss 139 dq35 140 dq39 41 dq16 42 dq20 141 dq40 142 dq4 4 43 dq17 44 dq21 143 vdd 144 vdd 45 vdd 46 vdd 145 dq41 146 dq45 47 dqs2 48 dm2 147 dqs5 148 dm5 49 dq18 50 dq22 149 vss 150 vss 51 vss 52 vss 151 dq42 152 dq46 signals in brackets are not used on module, but may be connected on the socket
data sheet rev.1.0 30.05.2012 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 4 ch C 9552 bronschhofen fax: +41 (0) 71 9 13 03 15 email: info@swissbit.com of 13 pin # front side pin # back side pin # front side pin # back side 53 dq19 54 dq23 153 dq43 154 dq47 55 dq24 56 dq28 155 vdd 156 vdd 57 vdd 58 vdd 157 vdd 158 /ck1 59 dq25 60 dq29 159 vss 160 ck1 61 dqs3 62 dm3 161 vss 162 vss 63 vss 64 vss 163 dq48 164 dq 52 65 dq26 66 dq30 165 dq49 166 dq53 67 dq27 68 dq31 167 vdd 168 vdd 69 vdd 70 vdd 169 dqs6 170 dm6 71 cb0 72 cb4 171 dq50 172 dq54 73 cb1 74 cb5 173 vss 174 vss 75 vss 76 vss 175 dq51 176 dq55 77 dqs8 78 dm8 177 dq56 178 dq60 79 cb2 80 cb6 179 vdd 180 vdd 81 vdd 82 vdd 181 dq57 182 dq61 83 cb3 84 cb7 183 dqs7 184 dm7 85 nc 86 nc ( / reset) 185 vss 186 vss 87 vss 88 vss 187 dq58 188 dq62 89 ck2 90 vss 189 dq59 190 dq63 91 /ck2 92 vdd 191 vdd 192 vdd 93 vdd 94 vdd 193 sda 194 sa0 95 nc ( cke1 ) 96 cke 0 195 scl 196 sa1 97 nc 98 nc (ba2) 197 vddspd 198 sa2 99 a12 100 a11 199 vddid 200 nc
data sheet rev.1.0 30.05.2012 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 5 ch C 9552 bronschhofen fax: +41 (0) 71 9 13 03 15 email: info@swissbit.com of 13 functional block diagramm 512mb ddr sdram sodimm 1rank; non - ecc
data sheet rev.1.0 30.05.2012 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 6 ch C 9552 bronschhofen fax: +41 (0) 71 9 13 03 15 email: info@swissbit.com of 13 dc electrical characteristics and operating conditions (0c t a + 70c; v dd = +2.5v 0.2v, v ddq = +2.5v 0.2v) see note 1 on page 9 parameter/ condition symbol min max units supply voltage v dd 2.3 2.7 v i/o supply voltage v dd q 2.3 2.7 v i/o reference voltage v ref 0.49 x v dd q 0.51x v dd q v i/o termination vo ltage (system) v tt v ref C 0.04 v ref + 0.04 v input high (logic 1) voltage v ih (dc) v ref + 0.15 v dd + 0.3 v input low (logic 0) voltage v il (dc) - 0.3 v ref C 0.15 v input leakage current any input 0v v in v dd, v ref pin 0v v in 1.35v i i - 16 16 a output leakage current (dq s are disabled; 0v v out v ddq ) i oz - 40 40 a output levels: high current ( v out = v ddq - 0.373v,minimum v ref, minimum v tt ) low current ( v out =0.373v, maximum v ref, maximum v tt ) i oh i ol - 16.8 16.8 - - ma ma ac input operating conditions (0c t a + 70c; v dd = +2.5v 0.2v, v ddq = +2.5v 0.2v) see note 1 on page 9 parameter/ condition symbol min max units input high (logic 1) voltage v ih (ac) v ref + 0.310 - v input low (logic 0) voltage v il (ac) - v ref - 0.310 v i/o reference voltage v ref(ac) 0.49 x v dd q 0.51x v dd q v capacitance parameter symbol min max units input/output capacitance: dq , dqs c 10 4.0 5.0 pf input capacitance: command and address c 11 18.0 27.0 pf input capacitance: /s 0,1 c 11 18.0 27.0 pf input capacitance: ck, /ck c 12 10.0 14.0 pf input capacitance: cke c 13 18.0 27.0 pf
data sheet rev.1.0 30.05.2012 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 7 ch C 9552 bronschhofen fax: +41 (0) 71 9 13 03 15 email: info@swissbit.com of 13 i dd specifications and conditions ( 0c t a + 70c; v ddq = +2.5v 0.2v, v dd = +2.5v 0.2v ) see note 1 on page 9 parameter & test condition symb. max. 3200 - 3033 2700 - 2533 unit operating current *) : one device bank; active - precharge; t rc = t rc (min); t ck = t ck (min); dq, dm and dqs inputs changing once per clock cycle; address and control inputs changing once every two clock cycles i ddo 1395 1170 ma operating current : *) one device bank; active - read - precharge; burst = 2; t rc = t rc (min); t ck = t ck (min);i out = 0ma; address and cont rol inputs changing once per clock cycle i dd1 1665 1440 ma precharge power - down standby current: all device banks idle; power - down mode; t ck = t ck (min); cke = (low) i dd2p 45 45 ma idle standby current: cs# = high; all device banks idle; t ck = t ck (min ); cke= high; address and other control inputs changing once per clock cycle. v in = v ref for dq, dqs, and dm i dd2f 495 405 ma active power - down standby current: one device bank active; power - down mode; t ck = t ck (min);cke = low i dd3p 405 315 ma active standby current: cs# = high; cke = high; one device bank; active - precharge; t rc = t ras (max); t ck = t ck (min); dq, dm and dqs inputs changing twice per clock cycle; address and other control inputs changing once per clock cycle i dd3n 540 450 ma operating current: burst = 2; reads; continous burst; one bank active; address and control inputs changing once per clock cycle; t ck = t ck (min); i out = 0ma i dd4r 1710 1485 ma operating current: burst = 2; writes; continuous burst; one device bank active; addres s and control inputs changing once per clock cycle; t ck = t ck (min); dq, dm, and dqs inputs changing twice per clock cycle i dd4w 1755 1575 ma auto refresh current t r f c = t r f c (min) i dd5 3105 2610 ma t r f c = 7.8125 s i dd 5a 99 90 ma self refresh curren t: cke 0.2v i dd 6 45 45 ma operating current *) : four device bank interleaving reads (bl =4) with auto precharge, t rc = t rc (min); t ck = t ck (min); address and control inputs change only during active read, or write commands i dd 7 4050 3645 ma *) value calculated as one module rank in this operating condition, and all other module ranks in idd2p (cke low) mode.
data sheet rev.1.0 30.05.2012 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 8 ch C 9552 bronschhofen fax: +41 (0) 71 9 13 03 15 email: info@swissbit.com of 13 ddr sdram component electrical characteristics and recommended ac operating conditions (0c t a + 70c; v ddq = +2.5v 0.2v, v dd = +2.5v 0.2v) see note 1 on page 9 ac characteristics 3200 - 3033 2700 - 2533 parameter symbol min max min max unit access window of dq s ck/ck# t ac - 0. 7 0 +0. 7 0 - 0.70 +0.70 ns ck high - level width t ch 0.45 0.55 0.45 0.55 t ck ck low - level width t cl 0.45 0.55 0.45 0 .55 t ck clock cycle time cl=2.0 t ck (2.0) 7.5 13.0 7.5 13.0 cl=2.5 t ck (2.5) 6.0 13.0 6.0 13.0 ns cl= 3.0 t ck (3.0) 5.0 13.0 ns dq and dm input hold time relative to dqs t dh 0.40 0.45 ns dq and dm input setup time relative to dqs t ds 0.4 0 0.45 ns dq and dm input pulse width ( for each input ) t dipw 1.75 1.75 ns access window of dqs from ck/ck# t dqsck - 0.6 +0.6 - 0.6 +0.6 ns dqs input high pulse width t dqsh 0.35 0.35 t ck dqs input low pulse width t dqsl 0.35 0.35 t ck dqs C t dqsq 0.40 0.45 ns write command to first dqs latching transition t dqss 0.72 1.28 0.75 1.25 t ck dqs falling edge to ck rising - setup time t dss 0.2 0.2 t ck dqs falling edge from ck rising - hold time t dsh 0.2 0.2 t ck half clock period t hp t ch, t cl t ch, t cl ns data - out high - impedance window from ck/ck# t hz +0.7 +0.7 ns data - out low - impedance window from ck/ck# t lz - 0.7 - 0.7 ns address and control input hold time ( fast slew rate ) t ihf 0.6 0.7 5 ns address and control input setup time ( fast slew rate ) t isf 0.6 0.75 ns address and control input hold time ( slow slew rate ) t ihs 0.7 0.8 ns address and control input setup time ( slow slew rate ) t iss 0.6 0.8 ns load mode register co mmand cycle time t mrd 10 12 ns adress and control input pulse width (for each input) t ipw 2.2 2.2 ns dq - dqs hold, dqs to first dq to go non - valid, per access t qh t hp - t qhs t hp - t qhs ns data hold skew factor t qhs 0.5 0.6 ns
data sheet rev.1.0 30.05.2012 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 9 ch C 9552 bronschhofen fax: +41 (0) 71 9 13 03 15 email: info@swissbit.com of 13 ac characteristics 3200 - 3033 2700 - 2533 parameter symbol min max min max unit active to precharge command t ras 40 70.000 42 70.000 ns active to read with auto precharge command t rap 15 15 ns active to active/auto refresh command period t rc 55 6 0 ns auto refresh command period t rfc 70 72 ns active to read or write delay t rcd 15 18 ns precharge command period t rp 15 18 ns dqs read preamble t rpre 0.9 1.1 0.9 1.1 t ck dqs read postamble t rpst 0.4 0.6 0.4 0.6 t ck active bank a to active b ank b command t rrd 10 12 ns dqs write preamble t wpre 0.25 0.25 t ck dqs write preamble setup time t wpres 0 0 ns dqs write postamble t wpst 0.4 0.6 0.4 0.6 t ck write recovery time t wr 15 15 ns internal write to read command delay t wtr 2 1 t ck data valid output window na t qh - t dqsq t qh - t dqsq ns refresh to refresh command interval t refc 70.3 70.3 s average periodic refresh interval t refi 7.8 7.8 s terminating voltage delay to v dd t vtd 0 0 ns exit self refresh to non - read comman d t xsnr 70 75 ns exit self refresh to read command t xsrd 200 200 t ck note 1: values for ac timing, i dd , and electrical ac and dc characteristics might have been collected within the standard temperature range and at nominal reference/supply volt age levels, but the related specifications and device operation are guaranteed for the full voltage range specified and for the corresponding field of operation according to the actual temperature grade of the module (extended e, i or w; refer to the envir onmental conditions for more details).
data sheet rev.1.0 30.05.2012 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 10 ch C 9552 bronschhofen fax: +41 (0) 71 9 13 03 15 email: info@swissbit.com of 13 serial presence - detect matrix byte description 3200 - 3033 2700 - 2533 0 number of spd bytes used 0x80 1 total number of bytes in spd device 0x08 2 fundamental memory type 0x07 3 number of row addresses on assembly 0x0d 4 number of column addresses on assembly 0x0b 5 number of physical banks on dimm 0x01 6 module data width 0x40 7 module data width (continued) 0x00 8 module voltage interface levels (v ddq ) 0x04 9 sdram cycle time, (t ck ) (cas latency =2.5 (2700 , 2100) ; cl=3* (3200) 0x50 0x60 10 sdram access from clock, (t ac ) (cas latency =2.5 (2700, 2100); cl=3* (3200)) 0x70 0x70 11 module configuration type 0x0 0 12 refresh rate/ type 0x82 13 sdram device width (primary sdram) 0x08 14 error - checking sdram data width 0x00 15 minimum clock delay, back - to - back random column access 0x01 16 burst lengths supported 0x0e 17 number of banks on sdram device 0x04 18 cas latencies supported 0x1c 0x0c 19 cs latency 0x01 20 we latency 0x02 21 sdram module attr ibutes 0x20 22 sdram device attributes: general 0xc0 23 sdram cycle time, (t ck ) (cas latency=2(2700, 2100) cl=2,5*(3200)) 0x60 0x75 24 sdram access from ck, (t ac ) (cas latency=2(2700, 2100) cl=2.5*(3200) 0x70 0x7 0 25 sdram cycle time, (t ck ) (cas latenc y=1.5(2700, 2100) cl=2*(3200)) 0x75 0x00 26 sdram access from ck, (t ac ) (cas latency=1.5(2700, 2100) cl=2*(3200) 0x75 0x00 27 minimum row precharge time, (t rp ) 0x3c 0x48 28 minimum row active to row active, (t rrd ) 0x28 0x30 29 minimum ras# to cas# dela y, (t rcd ) 0x3c 0x48 30 minimum ras# pulse width, (t ras ) 0x28 0x2a 31 module bank density 0x80
data sheet rev.1.0 30.05.2012 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 11 ch C 9552 bronschhofen fax: +41 (0) 71 9 13 03 15 email: info@swissbit.com of 13 serial presence - detect matrix (continued) byte description 3200 - 3033 2700 - 2533 32 address and command setup time, (t is ) 0x60 0x 80 33 address and coomand h old time, (t ih ) 0x60 0x 80 34 data/data mask input setup time, (t ds ) 0x40 0x45 35 data/data mask input hold time, (t dh ) 0x40 0x45 36 - 40 reserved 0x00 41 min active auto refresh time (t rc ) 0x37 0x3c 42 minimum auto refresh to active/ auto refresh comman d period, (t rfc) 0x46 0x48 43 sdram device max cycle time (t ckmax ) 0x28 0x30 44 sdram device max dqs - dq skew time (t dqsq ) 0x28 0x2 d 45 sdram device max read data hold skew factor (t qhs ) 0x50 0x 6 0 46 - 61 reserved 0x00 62 spd revision 0x10 63 checksum for bytes 0 - 62 tbd tbd 64 manufacturer`s jedec id code 7f 65 manufacturer`s jedec id code 7f 66 manufacturer`s jedec id code 7f 67 manufacturer`s jedec id code (continued) da 72 manufacturing location x 73 - 90 module part number (ascii) sdn06464k1b f1 mt - xx 91 pcb identification code x 92 identification code (continued) x 93 year of manufacture in bcd x 94 week of manufacture in bcd x 95 - 98 module serial number x 99 - 127 manufacturer - specific data (rsvd) x part number code s d n 064 64 k 1 b f 1 mt - 50 * r 1 2 3 4 5 6 7 8 9 10 11 12 13 *rohs compl. swissbit ag ddr - 400mhz sdram d dr 200 pin unbuffered 2.5v chip vendor ( micron ) depth (512mb) 1 module rank width chip rev. f pcb - type ( so200rcb ) chip organisation x8 * optional / additional information
data sheet rev.1.0 30.05.2012 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 12 ch C 9552 bronschhofen fax: +41 (0) 71 9 13 03 15 email: info@swissbit.com of 13 revision history revision changes date 1.0 initial revision 30.05 .2012
data sheet rev.1.0 30.05.2012 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 13 ch C 9552 bronschhofen fax: +41 (0) 71 9 13 03 15 email: info@swissbit.com of 13 locations swissbit ag industriestrasse 4 ch C 9552 bronschhofe n switzerland phone: +41 (0)71 913 03 03 fax: +41 (0)71 913 03 15 _____________________________ swissbit germany gmbh wolfener strasse 36 d C 12681 berlin germany phone: +49 (0)30 93 69 54 C 0 fax: +49 (0)30 93 69 54 C 55 _____________________________ swissbit na, inc. 1202 e. winding creek drive eagle, id 83616 usa phone: +1 208 870 4525 fax: +1 208 870 4525 _____________________________ swissbit japan, inc. 3f core koenji, 2 - 1 - 24 koenji - kita, suginami - ku, tokyo 166 - 0002 japan phone: +81 3 5356 3511 fax: +81 3 5356 3512 _____________________________

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